A phase synchronizing circuit (PLL) frequency synthesizer is widely used in generating a clock on a side of receiving serial transmission, generating a clock of a semiconductor integrated circuit or the like. In PLL, a phase comparator is used for adjusting phases between a feedback clock and a reference clock. The phase comparator compares the phases of the feedback clock and the reference clock, and outputs up/down signals in accordance with a delay or an advance in the phases therebetween.
The phase comparator is provided with a mechanism of outputting a short up signal and a short down signal even when a phase difference between the feedback clock and the reference clock is small in order to prevent a dead zone. JP-A-2004-357076 shows a phase comparator of comparing a phase of a first input signal and a phase of a second input signal, which is a phase comparator having a first delay circuit of outputting a first delay signal by delaying a first input signal, a second delay circuit of outputting a second delay signal by delaying a second input signal, a first phase comparing circuit which is inputted with the first input signal and the second delay signal, and in which when a phase of the first input signal is more advanced than a phase of the second delay signal, a first output pulse in correspondence with the advance is outputted, and a second phase comparing circuit which is inputted with the second input signal and the first delay signal, and in which when a phase of the second input signal is more advanced than a phase of the first delay signal, a second output pulse in correspondence with the advance is outputted, showing a phase comparator which can prevent generation of a dead zone by outputting a minimum pulse even when the phases coincide with each other by a simple constitution.